Credence is done. The ARM64 engineering has been both incredible and exhausting, but it's the last backend I planned to support. The work on x86-64 and ARM64 together has been remarkable to say the least:

It is my Magnum Opus

That's the 2025-2026 github commit graph. Many 8+ hours days, and a few too many sleepless nights. It is my Magnum Opus. A milestone of professional and personal research since the idea was first conceived. The first commit in the parser is about 7 years old. Since then, I've designed languages and even built compilers at my workplace.

AArch64 is the Future

The differences in CPU design, register file, and ISA between arm64 and x86-64 make me want to throw my $4000 PC away. It is eye-opening. No wonder Apple's M series laptops are so great.

ARM64 has 32 128-bit vector registers. You read that right, 32. They're available for vector instructions, SIMD, and SVE/SVE2. Further, it has 31 separate, orthogonal general-purpose registers that are 64bits wide. Truthfully, I don't think it matters how much money you spend on an x86-64 CPU - it can never compete due to historical limitations. The word size of x86-64 is still 16 bits. That's two bytes, with 16 general-purpose registers - and most with a specialization.

I had to rewrite a lot of the code to make better use of arm64. I can't tell if it was better to start with x86-64 or not; almost everything changed.

For what it's worth, it led to some beautiful C++ code. I wanted to reuse as much as possible, so each backend roughly follows the same design. Each with a memory access mediator or "facade", specialized accessor and inserter types for data objects and algebraic operators, a pushdown stack, and the IR instruction visitor. You can read more about the backend overview here.

I recommend you read up on RISC vs CISC, there's a ton of literature on the topic!

I'm exhausted, to say the least. My next project will be something completely different, something closer to hardware.

Robotics, maybe?